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Sold Out. This manual contains the following chapters:. Pref ace: About This Guide. Additional Resour ces. T o find additional documentatio n, see the Xilinx website at:. T o search the Answer Da tabase of silicon, softw are, and IP questions and answ ers, or to. Intr oduction and Overview. Depending on specific requirements, choose th e Xilinx development board that best suits. The board highlights thes e features:. Adv anced Spar tan-3 Generation De velopment Boards.
For mor e. Chapter 1: Introd uction and Overview. Ke y Components and Features. The key features of the Spartan-3E Starter Kit boa rd ar e:. A few system-level design trade-of fs were r e quired in order to pr ovide the Spartan-3E. Starter Kit board with the most functionality. A typical FPGA application us es a single no n-volatile memory to store configuration.
The extra. The on-chip circuitry simplifies the devi ce programming expe rience. In typical. V oltages f or all Applications. However , the starter kit. Similarly , the. The slide switches ar e located in the lower ri ght corner of the board and are labeled SW3. Switch SW3 is the left-most switch, and SW 0 is the right-most switch. The switches typically exhibit about 2 ms of mechanical bounce an d there is no active.
Figure 2- 1: Four Slide Switc hes. Chapter 2: Switches, Button s, and Knob. The push buttons are lo cated in the lower left corner of the. FPGA pins that connect to the push buttons appear in par entheses in Figure and the. Pressing a push button connects the asso ciated FPGA pin to 3. Figure 2- 5 shows how to specify a pull-down resistor within the. There is no active debounci ng circuitry on the push button. Rotary Pus h-Button Switch. Figur e provides the UCF constraints for the four push-button switches , including the.
The rotary push-button switch is located in th e center of the four individual push-button. The switch produces thr ee outputs. The two shaft. The rotary push-button switch integrates two differ ent functions. The switch shaft rotates. The shaft can also be pr essed, acting as a. Use an int ernal pull-down r esi stor within the FPGA pin to. Figure shows how to specify a pull-down resistor within the UC F. There is no active debouncing cir cuitry on the push button.
Rotar y Shaft Encoder. In principal, the rotary shaft en coder behaves much like a cam, connect ed to central shaft. Rotating the shaft then operates tw o push-button switches, as shown in Figure Depending on which way the shaft is r otated, one of the switches opens before the other. Likewise, as the r otation continues, one switch closes befor e the other. However , when the. Closing a switch connects it to g round, generating a logic Low.
When the switch is open, a. The UCF constraints. As shown in Figure , the. Figure 2- 7: Basic exa mple of rota ry shaft encoder cir cuitry. See the UCF file f or details on. Each LED has one side connecte d to ground an d the other side connected to a pin on the. T o light an individual LED, drive the. Figur e 1 provides the UCF constraints for the four push-button switches, including the. Alternatively , the FPGA. Figure A vailable Clock Inputs. Bank 0, Oscillator V oltage.
Controlled by J umper JP9. Chapter 3: Clock So urces. Cloc k Connections. As shown in Ta b l e 3 - 1 , each of the clock inputs also optimally connects to. V olta ge Control. Consequently , these clock resources ar e also contro lled by jumper JP9. By defaul t, JP9 is set. The on-boar d oscillator is a 3. The oscillator. A uxiliar y Cloc k Oscillator Socket. The pr ovided 8-pin socket accept s clock oscillators that fit the 8-pin DIP footprint.
Use this. Alternatively , use. T o provide a clock from an external sour ce, connect the input clock signal to the SMA. The FPGA can also generate a sing le-ended clock output or other high-speed. The clock input sources r equire two dif fer ent ty pes of constraints. Th e location constraints. The period constraints define the clock. Figur e provides the UCF constraints for the thr ee clock input sources , including the. The settings assume that jumper JP9 is set.
If JP9 is set for 2. Cloc k P er iod Constraints. An example constraint appears in. Figur e for the on-board 50 MHz clock oscillator. The ou tput duty cycle from the oscillator ranges. Define clock period for 50 MHz os cillator. Down configuration modes. Further , an FP GA application can dy namically load two. See the. Figur e P arallel NOR Flash memory.
Figure Detailed Configuration Options. Select between three on-board configuration sources. Platform Flash chip select User programmab le. Configuration Mode Jumper s. The configuration mode jumpers determine which configuration mode the FPGA uses. The CPL D is user-. Configuration Mode J umpers. Inserting a jumper gr ounds the associated mode pin. Insert o r remove individual. The CPLD controls addr ess.
Pr ess and release this button to r estart the. V ia a USB cable. Dir ect programming of the. Connecting the USB Cab le. The actual cable color might vary fr om the picture. When the board is power ed on, the. W indows operating system should recognize an d install the associated driver softwar e. When the USB cable driver is successfully inst alled and the boar d is correctly connected to. T o begin programming, connect the USB cable to t he starter kit boar d and apply power to.
Navigator , as shown in Figur e If not. Select the desired. This message can be safely. Dire ct programming to the FPGA. The steps pr ovided in this section desc r ibe how to set up the PROM file and how. The FPGA pr ovides an.
CCLK oscillator always starts at its slowest setting, appr oximately 1. Most external. PROMs support a higher fr equency. Increase the CCLK fr equency as appropriate to r educe. Right-click Generator Programming File in the Proce sses pane, as shown in. Figure 4- Left- click Properties. Click Configuration Options as shown in Figure 4 -1 1. Using the Configuration. Rate drop list, choose 25 to increase the internal CCLK oscillator to approximate ly. Click OK.
Figure Set Pr oper ties for Bitstrea m Generato r. T o regenerate the pr ogramming file, double-click Generate Programming File , as. Select from any. Enter the Location of. Select xcf04s. Click Finish. As shown in Figure , click OK to start selecting files. Select an FP GA bitstream file. Finally , click OK to continue.
JT A G circuitry , follow the step s outlined in this subsection. Figure : Switch to Boundar y Scan Mode. The programming softwar e again prompts for the PROM type to be pr ogrammed. Before programming, choose the pr ogramming options available in Figur e The Verify option checks. Both these options ar e recommended even though they increase overall. Click OK when finished. If programming. LED, also shown in Figure , lights up.
Character LCD Scr een. Once master ed, the LCD is a practical way to display a variety of information using. However , these displays ar e not fast. Scr olling the. Compar ed with the. A PicoBlaze processo r efficiently. Ta b l e 5 - 1 shows the interface character LCD interface signals. V oltage Compatibility. However ,. The character LCD. Most applications treat the LCD as a write-. Interaction with In tel StrataFlash.
Conversely , when. X X 0 LCD write access only. Full access to StrataFla sh. X 0 X StrataFlash in byte-wide x8 mode. Upper address lines. UCF Location Co nstraints. The controller has three internal memory regions, each with a specific purpose. The charact er code stored in a DD.
RAM location references a specific characte r bitmap stored either in the predefined CG. Figur e shows the default address for the 32 char acter locations on the display. The second line of. Character Display Ad dresses Undisplayed. Locations 0x10 through 0x27 and 0x 50 through 0x67 can be used to stor e other. Alte rnatively , these locations can also stor e characters that can only. Mode Set command. The character. DD RAM location.
Each custom character location consis ts of a 5-dot by 8-line bitmap, as shown in. Lower Data Nibb le. Figur e provides an example, creating a special checkerbo ard character. The custom. DD RAM location is 0x The upper three ad dress bits point to. The lower thr ee address bits point to the row addr ess for the. Only the. The eighth. Ta b l e 5 - 3 summarizes the a vailable LCD contr oller commands and bit definitions.
The upper nibble is transferr ed first, followed by the lower nibble. Upper Nibble Lower Nibble. Upper Nibble Lower Nibb le. Clear Display 0 0 0 1. Return Curso r Home 0 0 1 -. Clear the display and return the cursor to the home position, the top-left corner. Clears all option. Set command. Retur n Cursor Home. Return the cursor to the home position, th e top-left corner. DD RAM contents are.
Also re turns the displa y being sh ifted to the origina l position, shown in. The display is r eturned to it s. The cursor or blink move to the top-left character location. Sets the cursor move direction and specif ies whether or not to shift the display.
These operations are performed during data r eads and writes. Function Set 1 0 - -. The cursor or blink position moves accor dingly. Display is turned on or off, contr olling all ch aracters, cursor and cursor position character. The cursor uses the five dots on the bottom li ne of the character. The cursor appears as a. Cursor and Displa y Shift.
Shift cur sor. This function positions the cursor in order to modify an individual character , or to scroll. The cursor automa tically moves to the second line when it. The first and second line dis plays. When the displayed data is shifted repeatedly , both lines move horizontally.
The second. Appears as thou gh the cursor position remains constant. Sets interface data length, number of display lines, and charact er font. The Starter Kit board supports a single function set with value 0x After this command, all subseque nt read or write operations to the display are to or fr om. The addresses for displayed characters appear in Figure Read the Busy flag BF to determine if an i n ternal operation is in progress, and r ead the. The next instruction is not.
This command also r eturns the present value of address counter. The addr ess counter is. The s pecific context depends on the most. Address command. The addr ess counter is decremented by one. The address counte r is incremented by o ne. Shift the entir e display to the le ft. Th e cursor follows the display shift.
Shift the entir e display to the r ight. After the write operation, the address is automati cally incremente d or decremented by 1. The entry mode al so determines display s hift. After the read operation, the address is au tomatically incremented or decr emented by 1. However , a displa y shift is not executed. F our-Bit Data Interface. The board uses a 4-bit data interface to the character LCD.
Figur e illustrates a write operation t o the LCD, showing the mi nimum times allowed. The ena ble signal must remain High for ns or longer—the equivalent of T ransf erring 8-Bit Data ov er the 4-Bit Interf ace. After initializi ng the display and establis hing communication, al l commands and data. Each 8-bit transfer must be decomp osed into two 4-bit transfers, spaced apart.
The upper nibble is transferr ed first, followed by. This delay must be increased to 1. Initializing the Displa y. After power-o n, the display must be initialized to establish the requir ed communication. The initialization sequence is si mple and ideally suited to the highly-eff icient After initialization, the PicoBlaze controller is available. P ow er-On Initialization. The initialization sequence first establishes that the FPGA application wishes to use the.
The 15 ms interval is , clock cycles at 50 MHz. Displa y Configuration. After the power-on initialization is completed, the four-bit interface is now es tablished. The next part of the sequence configures the display:. Allow at least 1. Writing Data to the Displa y. T o write data to the display , specify the start address, followed by on e or m o r e d a t a v al ue s. The 8-bit. If the address counter is configured to auto-i ncrement, as described earlier , the application.
Continuing to write characters, however , eventually falls of f the end of the first dis play. The additional characters do not automati cally appear on the second line because the. DD RAM map is not consecutive from the first line to the second. Disab ling the Unused LCD. As shown in Figur e , the VGA connector is the left-most. Each color line has. V er tical Sync. VGA signal timing is specified , published, copyrighted, and sold by the V ideo Electronics.
The foll owin g VGA system and timing in formation is. For more pr ecise information or for information on higher VGA frequencies, refer to. LCDs use an array of switches. Although the following. W ithin a CRT display , current waveforms pass through the coils to pr oduce magnetic fields. As shown in Figure 6- 2 , information is. Much of the potential display time is therefore lost in blanking periods when the.
T able 3-Bit Display Color Co des. The display resol ution defines the size of the beams, the frequency at which the beam. V ideo data typically comes from a video r efres h memory with one or mor e bytes assigned. The controller indexes into. The controller th en retrieves. Stable current ramp: Inf ormation is. Retrace: No. T otal horizontal time. Horizontal displa y time.
The pixel clock defines the time availabl e to display one pixel of informati on. The VS signal. The number of horizont al lines displayed at a given r efresh frequency defines the. V GA Signal Timing. The signal timings in Ta b l e 6 - 2 are derived for a pixel by r ow display using a. Fi gure shows the r elation between each of. The timing for the sync pulse width T PW and front and back por ch. The fr ont. Information cannot be.
Generally , a counter clocked by the pixel cl ock controls the horizontal timing. This counter tracks the curr ent pixel display. A separate counter tracks the vertical timing. The vertical-sync counter incr ements with. This counter tracks the current. These two continuously running counters form the addr ess into a video. No time relationship is s pecified between the onset of the HS pulse and the onset of the VS. Symbol P arameter. V er tical Sync Horizontal Sync.
Time Clocks Lin es Time Clocks. T S Sync pulse time The DCE-style port. Null modem, gender changers,. Figure 7- 1: RS Serial P or ts. M13 U8 M14 R7. Chapter 7: RS Serial P or ts. Hardwar e flow control is not supported on the connector. Only pins 1 and 5 of the. Both a mouse and keyboard drive the bus with identical signal timings and both use 1 1-bit. However , the data packets are.
Furthermor e, the keyboar d interface. The clock and data signals are. The timing defines signal requir em ents for mouse-to-host communications and. As shown in Figure , the attached keyboard or. Key bo a rd. The keyboard uses open-collector drivers so th at either the keyboard or the host can drive.
If the host never sends data to the keyboard, the n the host can use simple. Nearly all. Each key has a singl e, unique scan code that is s ent. The scan codes for most keys appear in. If the key is pr essed and held, the keyboar d repeatedly sends the scan code every ms or.
The keyboard sends the same scan code, r egardless if a key has. The host determines which character is intended. Symbol Param eter Min Max. Keyb oa rd. The host can also send commands and data to the keyboard. Ta b l e 8 - 3 provides a short list. The keyboar d sends commands or data to the ho st only when both the data and clock lines.
Because the host is the bus master , the keyboard checks whether the host is sending data. The clock line can be used as a clear to send signal. If the host pulls. When the keyboard sends data, it ge nerates 1 1 clock transitions at around 20 to. E0 E0 6B. The keyboar d acknowledges receipt of an.
EE Echo. F3 Set scan code repeat rate. FE Resend. Upon receiving a resend command, the ke yboard resends the last scan code sent. FF Reset. Resets the keyb oard. A mouse generates a clock and data signal when moved; otherwise, these signals r emain. High, indicating the Idle state.
Each time the mouse is moved, the mouse sends three 1 1-bit. Each data. The thr ee 8-bit data fields contain movement data as shown in. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz. Likewise, mo ving the mouse up gene rates a positive value. The XS and YS bits in the. The magnitude of the X and Y values repr esent the rate of mouse movement. The larger the. If the mouse moves continuously , the bit transmissions repeat.
The L and R fiel ds in the status by te indicate Left and Right bu tton presses. Idle state Idle state. Star t bit Star t bit. Stop bit Stop bit Stop bit. Mouse status byte X direction byte Y direction byte. Although the.
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Configuration Mode Jumpers. Connecting the USB Cable. Chapter 5. Character LCD Screen. Voltage Compatibility. Interaction with Intel StrataFlash. LCD Controller. Memory Map. Command Set. Four-Bit Data Interface. Transferring 8-Bit Data over the 4-Bit Interface. Initializing the Display. Writing Data to the Display. Disabling the Unused LCD.
VGA Signal Timing. Chapter 8. Voltage Supply. Chapter 9. SPI Communication. Interface Signals. SPI Communication Details. Communication Protocol. Digital Outputs from Analog Inputs. Programmable Pre-Amplifier. Programmable Gain. SPI Control Interface. Connecting Analog Inputs.
StrataFlash Connections. Shared Connections. Character LCD. SPI Data Line. Configuring from SPI Flash. Setting the Configuration Clock Rate. Additional Design Details. Variant Select Pins, VS. Jumper Block J Programming Header J Showing Slide 1 of 1. Sponsored Sponsored Sponsored.
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The Spartan-3E Starter Board provides a powerful and highly advanced self-contained development platform for designs targeting the Spartan-3E FPGA from. No information is available for this page. Xilinx Digilent Spartan-3E FPGA Starter Kit Board ; Brand new. $ ; Pre-owned. $ ; Make an offer: Brand New.